Item specifics
Description
STM32H723VGT6 Product Overview
STM32H723VGT6 is a Cortex-M7 MCU at 550 MHz with double-precision FPU, LQFP-100. 1 MB dual-bank Flash, 564 KB SRAM, USB OTG HS/FS (on-chip HS PHY), Ethernet MAC, CAN FD, dual Quad SPI, FMC (SDRAM), three 16-bit ADCs (5 Msps), two 12-bit DACs, two comparators, two op-amps, advanced motor control timers, GP/LP timers, RTC, 8×USART/UART, 5×SPI/I2S, 4×I2C, SDIO, SAI, SPDIF-Rx. 80 x 5 V-tolerant I/Os. 1.71–3.6 V, -40–85 °C. Compared to the STM32H723VET6 (512 KB Flash), this model doubles the Flash to 1 MB, providing ample code space for complex real-time control, industrial networking, and data processing — the top-tier 100-pin model in the H723 series.
STM32H723VGT6 Core Features
Core: Cortex-M7 550 MHz, DPFPU + L1 cache (16 KB I-cache + 16 KB D-cache)
Memory: 1 MB Dual-Bank Flash, 564 KB SRAM (incl. 128 KB DTCM)
Connectivity: Ethernet MAC, USB OTG HS/FS (on-chip HS PHY), CAN FD, SDIO, SAI, SPDIF-Rx, 8×USART/UART, 5×SPI/I2S, 4×I2C
Analog: 3×16-bit ADCs (5 Msps), 2×12-bit DACs, 2×Comparators, 2×Op-Amps
Motor Control: 2×Advanced Timers (PWM/Deadtime/Brake), multiple GP/LP timers
Memory Expansion: FMC (SDRAM/PSRAM/NOR/NAND), Dual Quad SPI
I/Os: 80 (5 V-tolerant)
Package: LQFP-100
Temperature Range: -40°C to 85°C
STM32H723VGT6 Applications
Industrial Control: Real-time controllers, PLCs, servo drives, industrial Ethernet gateways
High-Speed Communication: Ethernet/CAN FD/USB HS interface conversion and bridging
Audio & Consumer: Digital audio equipment, advanced consumer electronics
Motor Control: High-precision FOC, multi-axis servo control
Portable Medical & Instrumentation: High-performance handheld devices, precision data acquisition
STM32H723VGT6 Key Advantages
550 MHz Cortex-M7 + DPFPU: Ultimate real-time processing and floating-point performance
1 MB Dual-Bank Flash: Large storage for safe firmware updates and complex applications
On-Chip USB HS PHY: Eliminates external HS PHY, simplifying design and BOM
Ethernet + CAN FD + Rich Connectivity: Single-chip for industrial networking and real-time communication
Dual Quad SPI + FMC: Flexible external memory expansion
80 I/Os in Compact 100-Pin Package: High-density interfaces, space-saving
1.71–3.6 V Wide Supply: Adaptable to various power scenarios
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FAQ
1. What is the difference between the STM32H723VGT6 and the STM32H723ZGT6, and what are the advantages of the LQFP‑100 package?
Both share the same 550 MHz Cortex‑M7 core, 1 MB dual‑bank Flash, 564 KB SRAM, and all digital peripherals. The main differences lie in the package and I/O count: the VGT6 uses an LQFP‑100 package (14 mm × 14 mm) with 82 usable I/Os, while the ZGT6 uses an LQFP‑144 package with 114 I/Os. The VGT6 is more compact, easy to hand‑solder, and ideal for PCB‑sensitive designs with moderate I/O needs. If your system does not require more than 82 I/Os, the VGT6 delivers identical computational performance and security features in a smaller footprint.
2. Is the LQFP‑100 package easy to solder? Is it suitable for low‑volume hand assembly?
Very easy. The LQFP‑100 has all pins exposed with a 0.5 mm pitch and can be drag‑soldered with a standard iron and flux—no hot‑air station required. It strikes an excellent balance between mass production and hand prototyping, making it ideal for hobbyists, students, and small teams. The 14 mm × 14 mm size offers great compactness while remaining highly manageable.
3. Does the 1 MB dual‑bank Flash support OTA updates, and how is safety ensured?
Fully supported. The dual‑bank architecture allows code execution from one bank while the other is erased and programmed. After a new firmware image is downloaded to the alternate bank and verified, a simple boot‑address switch completes the update. If a power loss or verification failure occurs, the system automatically rolls back to the original firmware, guaranteeing the device is never bricked. Combined with the on‑chip AES‑256 and SHA accelerators, fully secure encrypted updates can be implemented—ideal for industrial IoT gateways and critical infrastructure requiring reliable remote maintenance.
4. How is the 564 KB SRAM organized, and how does it benefit hard real‑time tasks?
The SRAM is carefully partitioned into 128 KB DTCM (Data Tightly Coupled Memory), 64 KB ITCM (Instruction Tightly Coupled Memory), 256 KB AXI SRAM, and 128 KB low‑power SRAM (retainable in Stop mode). DTCM and ITCM provide zero‑wait‑state CPU access for the lowest and most deterministic interrupt and control‑loop latency. The multi‑bank architecture allows DMA and the CPU to access different regions simultaneously without blocking, significantly boosting throughput when handling Ethernet, LCD refresh, and high‑speed ADC acquisition concurrently.
5. Can the Chrom‑ART accelerator and LCD controller be fully utilized in the LQFP‑100 package? Are there enough pins?
The Chrom‑ART (DMA2D) accelerator does not consume extra I/Os, so its functionality is package‑independent. However, the on‑chip TFT‑LCD controller (LTDC) requires many pins for a 24‑bit RGB interface; using a full 24‑bit interface would consume nearly half of the 82 available I/Os. You can still drive a 16‑bit display or use an SPI‑based smart screen to free up GPIOs. It is recommended to use STM32CubeMX for pin planning to strike a balance between graphics and other peripherals.
6. What hardware security features does the chip integrate? Is secure boot supported?
It includes a hardware true‑random‑number generator (TRNG), an AES‑256 encryption accelerator, and SHA‑1/SHA‑2 and HMAC hashing accelerators for efficient encryption and authentication. Together with the dual‑bank Flash and code readout protection (RDP), it can establish a complete chain of trust from secure boot to encrypted firmware updates, effectively preventing unauthorized firmware access or tampering. This is especially important in payment terminals, IoT security gateways, and industrial controllers where IP protection is essential.
7. What external memory types can be connected via FMC and dual QSPI? Is SDRAM supported?
The Flexible Memory Controller (FMC) supports standard 16/32‑bit SDRAM, allowing up to 256 MB of runtime memory expansion, and can also interface with parallel NOR/NAND Flash. The dual Quad SPI interfaces support memory‑mapped mode and can connect high‑speed NOR Flash (up to 512 Mbit) or HyperRAM for code, graphics, and file storage. Within the 100‑pin package, you can simultaneously bring out a 16‑bit SDRAM bus and both QSPI ports, building a highly flexible memory architecture.
8. What high‑speed communication interfaces does the chip offer? Can Ethernet, USB HS, and CAN FD be used concurrently?
It integrates a 10/100M Ethernet MAC (with IEEE 1588 precision time protocol), a USB 2.0 OTG high‑speed controller (480 Mbps), and up to three FDCAN controllers. All can operate simultaneously without conflicts and feature dedicated DMA to reduce CPU overhead. With careful pin‑multiplexing among the 82 I/Os, you can bring out Ethernet RMII, USB HS ULPI, and at least two CAN FD channels while still leaving room for other peripherals.
9. How should power and thermal management be handled at 550 MHz full load? Is the LQFP‑100 package reliable?
Typical power consumption at full load is around 1–1.5 W. The LQFP‑100 package has no exposed thermal pad, but effective heat dissipation can be achieved through a large ground copper pour under the chip, a multi‑layer PCB, and sufficient thermal vias—no external heatsink is required. The chip supports dynamic frequency scaling and multiple low‑power modes (Sleep, Stop, Standby) to significantly reduce power during idle periods. It is usually rated for the industrial temperature range (-40 °C to 85 °C), and with good thermal design, reliable long‑term operation can be ensured.
10. Is the software toolchain for the STM32H723VGT6 mature? Can I reuse code from previous STM32F4/F7 projects?
Very mature. It is fully compatible with the STM32Cube ecosystem, including the free STM32CubeMX graphical configuration tool, STM32CubeIDE integrated development environment, and the feature‑rich STM32CubeH7 firmware package. When migrating from STM32F4 or F7, a large portion of HAL code can be reused, with the main adjustments being peripheral configuration and memory mapping. ST also provides extensive example projects and middleware covering Ethernet, USB, graphics, and file systems to jump‑start development.