R128-S2 Allwinner Wireless Audio SoC Triple-Core 16MB PSRAM WiFi/BT QFN-80

Model:
R128-S2
Brand:
Allwinner
Package:
QFN-80
CPU:
XuanTie 64-bit RISC-V C906 @ 600MHz
Core:
Arm M33 Star @ 192MHz
DSP:
Cadence HiFi5 @ 400MHz
Embedded Memory:
1MB SRAM, 16MB PSRAM (8MB LS + 8MB HS), 16MB NOR Flash
Audio:
3×ADC, 2×DAC (24‑bit), 119dB SNR (DAC), 98dB SNR (ADC)
Communication Interfaces:
USB 2.0 DRD, 3×UART, 2×SPI, 2×TWI/I²C, 8×PWM, 7×GPADC, CIR RX/TX, LEDC
Applications:
Smart speakers, smart home hubs, voice-controlled appliances, display‑enabled interactive terminals, AIoT edge devices, children’s educational toys

R128-S2 Product Overview

The R128-S2 is a highly integrated, high-performance wireless audio SoC from Allwinner Technology, housed in a QFN-80 package (8×8mm, 0.35mm pitch). The chip features an innovative triple-core heterogeneous architecture, integrating a XuanTie C906 64-bit RISC-V application core (up to 600MHz), an Arm M33 Star real-time core (up to 192MHz), and a Cadence HiFi5 audio DSP (up to 400MHz). The chip integrates via SiP 1MB SRAM, 16MB PSRAM (8MB LS-PSRAM + 8MB HS-PSRAM), and 16MB NOR Flash. It also integrates a 2.4GHz 802.11b/g/n WLAN and dual-mode Bluetooth 5.0 subsystem, a voice and audio codec subsystem, and a power management unit (PMU). Designed for smart IoT and voice interaction applications, the R128-S2 is widely used in smart speakers, smart home hubs, voice-controlled home appliances, and display-equipped interactive terminals.


R128-S2 Core Features

The R128-S2 features a XuanTie 64-bit RISC-V C906 application core (up to 600MHz), an Arm M33 Star real-time core (up to 192MHz), and a HiFi5 audio DSP (up to 400MHz). The chip integrates 1MB SRAM, 8MB LS-PSRAM, 8MB HS-PSRAM, and 16MB NOR Flash via SiP. It supports 2.4GHz 802.11b/g/n WiFi and dual-mode Bluetooth 5.0 wireless connectivity, and integrates a 24-bit audio codec with 3 ADC channels and 2 DAC channels, achieving up to 119dB SNR for DAC playback and 98dB SNR for ADC recording. For display, it supports an RGB output interface (up to 1024×768@60fps) and a 2D graphics accelerator with up to 4-layer overlay. For video input, it features an 8-bit parallel CSI interface and a JPEG hardware encoder (up to 1920×1088). The chip also provides a rich set of communication interfaces, including USB 2.0 DRD, up to 3 UARTs, 2 SPIs, 2 TWI/I²C, up to 8 PWMs, up to 7 GPADC channels, CIR RX/TX, and an LEDC interface.


R128-S2 Applications

The R128-S2 is widely used in smart speakers, smart home control panels, 86‑box voice panels, voice-controlled home appliances (air conditioners, fans, lighting), display-equipped interactive terminals, children‘s educational toys, voice remotes, AIoT edge nodes, and security surveillance cameras.


R128-S2 Key Advantages

As the mid‑range model in Allwinner‘s R128 series, the R128-S2 delivers exceptional integration by combining an application processor, audio DSP, wireless connectivity, memory, and a PMU into a single chip. Its triple‑core heterogeneous architecture enables efficient task division: the RISC‑V core handles application processing, the Arm M33 core focuses on real‑time control and security, and the HiFi5 DSP independently manages audio algorithms, ensuring fast response while reducing main core workload. With 16MB PSRAM and 16MB NOR Flash integrated via SiP, the R128‑S2 requires minimal external components to build a complete system, greatly simplifying hardware design and lowering BOM cost. The high‑performance audio codec with up to 119dB SNR, combined with the powerful HiFi5 DSP, supports professional audio features such as far‑field voice wake‑up, echo cancellation, and noise suppression – already mass‑production validated in flagship products like Tmall Genie. The compact QFN-80 package (8×8mm) is ideal for space‑constrained portable devices and smart terminals, making the R128‑S2 a preferred choice for smart voice and AIoT edge applications.


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FAQ:

  1. What is the Allwinner R128‑S2 and what are its core specifications?
    The R128‑S2 is a dedicated wireless audio SoC featuring a unique triple‑core heterogeneous architecture: one Arm Cortex‑M33 for low‑power system control, one HiFi3 DSP for audio processing, and one RISC‑V core for wireless protocol stacks. It integrates 16 MB of on‑chip PSRAM, dual‑band Wi‑Fi (2.4 GHz 802.11b/g/n), Bluetooth 5.2 (both classic and BLE), and a rich set of audio interfaces, all in a compact QFN‑80 package. This all‑in‑one design targets smart speakers, wireless audio dongles, and voice‑assistant devices.

  2. What is the purpose of the triple‑core architecture? How do the three cores work together?
    The Arm Cortex‑M33 runs the main application and system management. The HiFi3 DSP handles all real‑time audio tasks—such as noise reduction, echo cancellation, and audio decoding—with high efficiency. The RISC‑V core is dedicated to the Wi‑Fi and Bluetooth protocol stacks, ensuring stable wireless connectivity without interfering with the other cores. This separation allows the R128‑S2 to deliver high‑quality audio streaming with low latency while maintaining reliable Wi‑Fi/BT links.

  3. Why does the R128‑S2 integrate 16 MB of PSRAM on the chip? Is it enough for audio applications?
    The on‑chip 16 MB PSRAM eliminates the need for an external DRAM chip, which simplifies PCB layout, reduces BOM cost, and shrinks the overall board area. This amount of PSRAM is sufficient to run a lightweight RTOS (such as FreeRTOS), the wireless protocol stacks, audio codecs, and a voice‑assistant SDK simultaneously. It is specifically sized for wireless audio products where the firmware footprint is well‑defined and a compact memory configuration is desired.

  4. What Wi‑Fi and Bluetooth capabilities does the R128‑S2 offer?
    The R128‑S2 supports 2.4 GHz Wi‑Fi 4 (802.11b/g/n) and Bluetooth 5.2 dual‑mode (classic BR/EDR and BLE). This enables simultaneous Wi‑Fi audio streaming and Bluetooth connectivity—for example, streaming music over Wi‑Fi while maintaining a Bluetooth connection for a remote control or a smartphone app. The integrated RISC‑V core manages the wireless stacks, offloading the main M33 core and the DSP.

  5. What audio interfaces and processing features does the R128‑S2 provide?
    The chip offers a comprehensive set of audio interfaces: I²S for external audio codecs (ADC/DAC), TDM for multi‑channel microphones, and PDM for digital MEMS microphones. The HiFi3 DSP can run advanced audio algorithms such as acoustic echo cancellation (AEC), beamforming, and multi‑band EQ. These features make the R128‑S2 ideal for smart speakers, soundbars, and voice‑controlled devices that require clear far‑field voice pickup and high‑fidelity audio playback.

  6. How does the R128‑S2 compare to other Allwinner audio SoCs like the R329 or R818?
    The R329 is an AI‑focused audio SoC with a dual‑core Arm Cortex‑A53, a powerful NPU, and external DDR memory, targeting high‑end smart speakers with local voice recognition. The R818 is a tablet processor adapted for audio applications. The R128‑S2 is purpose‑built for cost‑sensitive wireless audio products: it integrates the necessary PSRAM on‑chip, uses an efficient Cortex‑M33 instead of power‑hungry A‑series cores, and dedicates separate processors for audio DSP and wireless connectivity. Choose the R128‑S2 when you need a compact, low‑power, single‑chip Wi‑Fi/BT audio solution with minimal external components.

  7. What is the advantage of the QFN‑80 package for this wireless audio SoC?
    The QFN‑80 package has exposed perimeter pads that can be drag‑soldered with a standard soldering iron and visually inspected. It is far more prototyping‑ and small‑batch‑production‑friendly than BGA packages. Combined with the on‑chip PSRAM, the R128‑S2 enables a true single‑chip wireless audio module that can be manufactured by smaller contract assembly houses without X‑ray inspection, accelerating time‑to‑market and reducing production costs.

  8. What development tools and SDK does Allwinner provide for the R128‑S2?
    Allwinner provides an SDK based on FreeRTOS, including the necessary drivers for Wi‑Fi, Bluetooth, the HiFi3 DSP, and all audio interfaces. The SDK includes sample applications for a Wi‑Fi speaker, a Bluetooth audio receiver, and a voice‑assistant integration. The HiFi3 DSP is programmed using Cadence's Xtensa toolchain, while the Arm Cortex‑M33 uses standard GCC or Keil toolchains. This mature software ecosystem helps developers quickly prototype wireless audio products.

  9. Is the R128‑S2 suitable for battery‑powered devices? How much power does it consume?
    The R128‑S2 is designed for low‑power operation, with the Cortex‑M33 and the RISC‑V core consuming very little active power. In a typical Wi‑Fi audio streaming scenario, the total system power is under 1 W. Combined with the chip's sleep modes, it is well‑suited for battery‑powered portable speakers, wireless audio dongles, and battery‑operated voice‑assistant devices that need long runtimes.

  10. What are the most typical applications for the Allwinner R128‑S2?
    It is used in smart Wi‑Fi speakers, Bluetooth audio receivers, portable wireless speakers, voice‑assistant endpoints, wireless subwoofers, and any compact audio product that needs dual‑mode Wi‑Fi/BT connectivity, high‑quality audio DSP, and a small PCB footprint. Its single‑chip integration minimizes BOM and simplifies design, making it a popular choice for cost‑sensitive, high‑volume audio products.